Current overlay measurements are often not stable due to gate height variation within the polysilicon (poly) layer, which results from chemical mechanical polishing (CMP) of the poly layer. As a result of the over polishing, for example, the requisite contrast between layers is degraded, which produces overlay metrology noise and prevents accurate gate to trench block (TB) overlay data feedback to a scanner for correction.
A need therefore exists for methodology enabling reduced gate height variation of a poly layer after CMP for stable overlay measurements, and the resulting device.